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10-bit, 6-channel decimating lcd decdriver ? with level shifters ad8384 rev. 0 in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . product features high accuracy, high resolution voltage outputs 10-bit input r e solution laser trimmed outputs fast settling, hi gh voltage dri v e 30 ns sett ling ti me to 0.25% in to a 150 pf load slew rate 460 v / s outputs to within 1.3 v of sup p ly rails high update ra tes fast, 100 ms/s 10-bit input da ta updat e rate voltage controlled video refer e nc e (brightness), offset, an d full-sca l e (contrast) output l e vels flexible logic stsq/xfr allow parallel ad8 384 operation inv bit re verse s polarity of vi deo signal output short-circuit protection 3.3 v logic, 9 v to 18 v analog supplies 18 v level shift e rs for panel ti ming signals avail a ble in 80 -lead 12 mm 12 mm tqfp e - pad applic ati o ns lcd analog column dri v ers func tio n a l block di agram byp dyin diryin dirxin nrgin dxin enbx1in enbx2in enbx3in enbx4in clxin clyin moniti svrh svrl sdi scl sen vrh vrl r/l clk stsq xfr db(0:9) inv v1 v2 tstm clx cly clxn clyn monito ad8384 vao1 vao2 vid0 vid1 vid2 vid3 vid4 vid5 dy diry dirx nrg dx enbx1 enbx2 enbx3 enbx4 scaling control sequence control bias dacs 2-stage latch inv control 12-bit shift register dual dac s r 9 / 2 / 3 / 2 / 2 / 4 / 10 / 9 / 2 / 2 / 6 / 04512-0-001 fi g u r e 1 . produc t d e scripti o n the ad8384 d e cdr i v e r p r o v ides a fast, 10-b i t, la t c hed , d e ci ma ti n g d i gi tal i n p u t tha t d r i v e s si x h i gh v o l t a g e o u t p u t s. 10-b i t i n p u t w o r d s a r e lo ade d s e q u en t i a l ly in t o six s e p a ra t e h i g h s p e e d , b i p o la r d a cs. flexi b le dig i tal in p u t f o r m a t al lo ws s e v e ral ad8384s t o be us ed in p a ral l e l in hig h r e s o l u tio n dis p la ys. th e o u t p u t sig n al can b e ad j u st e d f o r dc r e f e r e n c e , sig n al in v e rsio n, a nd co n t rast fo r max i m u m f l ex i b i l i t y . i n teg r a t e d le vel shif ters co n v er t timin g sig n als f r o m a 3 v timin g co n t rol l er t o hig h v o l t a g e fo r l c d p a n e l t i mi n g i n p u ts. t w o s e r i a l in p u t, 8-b i t d a cs a r e in teg r a t e d t o p r o v ide dc r e f e r e n c e sig n als. d a c addr ess e s and 8 - b i t da t a a r e lo a d e d i n on e 12- b i t s e r i a l w o r d . the ad8384 is fa b r ica t e d o n t h e 26 v , fas t , b i p o la r xfhv p r o c es s de v e l o p e d b y analog d e v i ces, i n c. this p r o c es s p r o v ides fast in p u t log i c, b i p o l a r d a cs w i t h t r i mme d acc u rac y a nd fast s e t t ling, hig h vol t a g e, p r e c isio n dr i v e am plif iers o n t h e sa m e c h i p . the ad8384 dis s i p a t es 1.1 w no minal s t a t ic p o w e r . the ad8384 is o f f e r e d in a n 80 -lead 12 mm 12 mm t q fp e-p a d p a cka g e a nd o p er a t es o v er t h e 0c t o 85c co mm er c i al t e m p era t ur e ra ng e .
ad8384 rev. 0 | page 2 of 24 table of contents specifications ..................................................................................... 3 decdriver ...................................................................................... 3 level shifters ................................................................................. 5 level shifting edge detector ...................................................... 5 serial interface .............................................................................. 6 power supplies .............................................................................. 7 operating temperature ............................................................... 7 absolute maximum ratings ............................................................ 8 maximum power dissipation ..................................................... 8 operating temperature range ................................................... 8 overload protection ..................................................................... 8 exposed paddle ............................................................................. 8 pin configuration and function descriptions ............................. 9 timing characteristics ................................................................... 11 decdriver section ...................................................................... 11 level shifter section ................................................................... 12 level shifting edge detector .................................................... 13 serial interface ............................................................................ 14 functional description .................................................................. 15 accuracy ...................................................................................... 16 tstm controltest mode ...................................................... 16 grounded output mode ........................................................... 16 overload protection ................................................................... 16 3-wire serial interface ............................................................... 16 serial dacs ................................................................................. 16 level shifters ............................................................................... 16 applications ..................................................................................... 17 power supply sequencing ......................................................... 17 vbias generationv1, v2 input pin functionality ........... 18 applications circuit ................................................................... 18 pcb design for optimized thermal performance ............... 19 thermal pad design .................................................................. 19 thermal via structure design .................................................. 19 ad8384 pcb design recommendations ............................... 20 outline dimensions ....................................................................... 21 ordering guide .......................................................................... 21 revision history revision 0: initial version
ad8384 rev. 0 | page 3 of 24 specifications decdriver table 1. @ 25c, avcc = 15.5 v, dvcc = 3.3 v, t a min = 0c, t a max = 85c, vrh = 9.5 v, vrl = v1 = v2 = 7 v, unless otherwise noted parameter conditions min typ max unit video dc performance 1 t a min to t a max vde dac code 450 to 800 C7.5 +7.5 mv vcme dac code 450 to 800 C3.5 +3.5 mv video output dynamic performance t a min to t a max , v o = 5 v step, c l = 150 pf data switching slew rate 20% to 80% 460 v/s invert switching slew rate 20% to 80% 560 v/s data switching settling t ime to 1% 19 24 ns data switching settling t ime to 0.25% 30 50 ns invert switching settling time to 1% v o = 10 v step 75 120 ns invert switching settling time to 0.25% v o = 10 v step 250 500 ns invert switching overshoot v o = 10 v step 100 200 mv clk and data feedthrough 2 10 mv p-p all-hostile crosstalk 3 amplitude 10 mv p-p glitch duration 30 ns dac transition glitch energy dac code 511 to 512 0.3 nv-s video output characteristics output voltage swing avcc C voh, vol C agnd 1.1 1.3 v output voltagegrounded mode 0.25 v data switching delay: t 9 4 50 % of vidx 10 12 14 ns inv switching delay: t 10 5 50 % of vidx 13 15 17 ns output current 100 ma output resistance 22 ? reference inputs v1 range v2 (v1-0.25v) 5.25 avcc C 4 v v2 range v2 (v1-0.25v) 5.25 avcc C 4 v v1 input current C3 a v2 input current C14 a vrl range vrh vrl v1 C 0.5 avcc C 1.3 v vrh range vrh vrl vrl avcc v (vrhCvrl) range vfs = 2(vrh C vrl) 0 2.75 v vrh input resistance to vrl 20 k? vrl bias current C0.2 a vrh input current 125 a resolution coding binary 10 bits 1 vde = differential error voltage; vcme = common-mode error voltage; vfs = full-scale output voltage = 2 (vrh C vrl). see the section. accuracy 2 measured differentially on two outputs as clk and db(0:9) are driven and stsq and xfr are held low. 3 measured differentially on two outputs as the other four are transitioning by 5 v. measured for both states of inv. 4 measured from 50% of rising clk edge to 50% of output change. measurement is made for both states of inv. 5 measured from 50% of rising clk edge to 50% of output change. re fer to figure 7 for the definition.
ad8384 rev. 0 | page 4 of 24 decdriver (continued) parameter conditions min typ max unit digital input characteristics max. input data update rate 100 ms/s clk to data setup time: t 1 0 ns clk to stsq setup time: t 3 0 ns clk to xfr setup time: t 5 0 ns clk to data hold time: t 2 3 ns clk to stsq hold time: t 4 3 ns clk to xfr hold time: t 6 3 ns clk high time: t 7 3 ns clk low time: t 8 2.5 ns c in 3 pf i ih 0.05 a i il C0.6 a v ih 2 v v il 0.8 v v th 1.65 v
ad8384 rev. 0 | page 5 of 24 level shifters table 2. @ 25c, avcc = 15.5 v, dvcc = 3.3 v, t a min = 0c, t a max = 85c, vrh = 9.5 v, vrl = v1 = v2 = 7 v, unless otherwise noted parameter conditions min typ max unit level shifter logic inputs c in 3 pf i ih 0.05 a i il C0.6 a v th 1.65 v v ih 2.0 dvcc v v il dgnd 0.8 v level shifter outputs r l 10 k? v oh avcc C 0.45 avcc C 0.25 v v ol 0.25 0.45 v level shifter dynamic performance t a min to t a max output rise, fall timest r , t f dx, clx, clxn, enbx(1C4) c l = 40 pf 18.5 30 ns dy, cly, clyn c l = 40 pf 40 70 ns dirx, diry c l = 40 pf 100 150 ns nrg c l = 200 pf 35 50 ns c l = 300 pf 55 100 ns propagation delay timest 11 , t 12 , t 13 , t 14 dx, clx, clxn, enbx(1C4) c l = 40 pf 20 50 ns dy, cly, clyn c l = 40 pf 29 50 ns dirx, diry c l = 40 pf 60 100 ns nrg c l = 200 pf 25 55 ns c l = 300 pf 32 ns output skew enbx(1C4)t 15 , t 16 c l = 40 pf 2 ns dx to enbx(1C4)t 16 c l = 40 pf 2 ns dx to clxt 15 , t 16 , t 17 , t 18 c l = 40 pf 10 ns dy to cly, clynt 15 , t 16 , t 17 , t 18 c l = 40 pf 20 ns level shifting edge detector table 3. c l = 10 pf, t a min to t a max , unless otherwise noted parameter min typ max unit v il input low voltage agnd agnd + 2.75 v v ih input high voltage avcc C 2.7 avcc v v th lh input rising edge threshold voltage agnd + 3 v v th hl input falling edge threshold voltage avcc C 3 v v oh output high voltage dvcc C 0.45 dvcc C 0.25 v v ol output low voltage 0.25 0.45 v i ih input current high state 1.2 2.5 a i il input current low state C2.5 C1.2 a t 19 input rising edge propagation delay time 16 ns ?t 19 t 19 variation with temperature 2 ns t 20 input falling edge propagation delay time 12 ns ?t 20 t 20 variation with temperature 2 ns t r output rise time 5 ns t f output fall time 6 ns
ad8384 rev. 0 | page 6 of 24 serial interface table 4. @ 25c, avcc = 15.5 v, dvcc = 3.3 v, t a min = 0c, t a max = 85c, svrl = 4 v, svrh = 9 v, unless otherwise noted parameter conditions min typ max unit serial dac reference inputs svfs = (svrh C svrl) svrh range svrl < svrh svrl + 1 avcc C 3.5 v svrl range svrl < svrh agnd + 1.5 svrh C 1 v svfs range 1 8 v svrh input current svfs = 5 v C70 na svrl input current svfs = 5 v C2.8 C2.5 ma svrh input resistance 40 k? serial dac accuracy dnl svfs = 5 v, r l = C1.0 +1.0 lsb inl svfs=5 v, r l = C1.5 +1.5 lsb output offset error C2.0 +2.0 lsb scale factor error C4.0 +4.0 lsb serial dac logic inputs c in 3 pf i il C0.6 a i ih 0.05 a v th 1.65 v v ih 2.0 dvcc v v il dgnd 0.8 v serial dac outputs maximum output voltage svrh C 1 lsb v minimum output voltage svrl v vao1grounded mode 0.1 v i out 30 ma c load low range 6 0.002 f c load high range 1 0.047 f serial dac dynamic performance sen to scl setup time, t 20 10 ns scl, high level pulse width, t 21 15 ns scl, low level pulse width, t 22 10 ns sdi setup time, t 24 10 ns sdi hold time, t 25 10 ns scl to sen hold time, t 23 15 ns vao1, vao2 settling time, t 26 svfs = 5 v, to 0.5%, c l = 100 pf 1 2 s vao1, vao2 settling time, t 26 svfs = 5 v, to 0.5%, c l = 33 f 10 15 ms 6 outputs vao1 and vao2 are designed to drive very high capacitive loads. the load capacitance must be 0.002 f or 0.047 f. load capacitance in the range 0.002 f to 0.047 f causes the output overshoot to exceed 100 mv.
ad8384 rev. 0 | page 7 of 24 power supplies table 5. @ 25c, avcc = 15.5 v, dvcc = 3.3 v, t a min = 0c, t a max = 85c, svrl = 4 v, svrh = 9 v, unless otherwise noted parameter min typ max unit dvcc, operating range 3 3.3 3.6 v dvcc, quiescent current 40 50 ma avcc operating range 9 18 v total avcc quiescent current 70 85 ma operating temperature parameter conditions min typ max unit ambient temperature range, t a 7 still air 0 75 c ambient temperature range, t a 8 200 lfm 0 85 c junction temperature range, t j 100% tested 25 125 c 7 operation at high ambient temperature requ ires a thermally optimized pcb layout (see the applications sect ion), input data upd ate rate not exceeding 85 mhz, black- to-white transition 4v and c l 150 pf. in systems with limited or no airflow, the maximum ambie nt operating temperature is limited to 75c. for operation a bove 75c, see note 8 below. 8 in addition to the requirements stated in note 7 above, operation at 85c ambient temperat ure requires 200 lfm airflow.
ad8384 rev. 0 | page 8 of 2 4 absolute maximum ratings table 6. ad83 84 stress ratings 9 p a r a m e t e r r a t i n g supply voltages avccx C agndx 18 v dvcc C dgnd 4.5 v input voltages m a ximum digital input voltage dvcc + 0.5 v minimum digital input voltage dgnd C 0.5 v maximum analog input voltage avcc + 0.5 v minimum analog input voltages agnd C 0.5 v internal power dissip a tion 1 0 tqfp e-pad pac k age @ t a = 25c 4.16 w operating temperature range 0c to 85c storage temperature range C65c to +125c lead temperature range (soldering 10 sec) 300c 9 st re sse s a b ov e t h o se li st e d un d e r t h e abso lut e ma xi m u m r a t i n gs m a y ca use permanent d amage to the d e vice. this is a s t ress rating onl y; functional o p e r atio n o f the device at the s e o r any o the r co nd itio ns a b o v e tho se i n di ca t e d i n t h e op era t i o n a l sect i o n of this s p ecif ication is not impl i ed . e x po sure to the ab s o lute maximum ratings f o r e x te nde d pe rio d s may reduc e device relia b ility. 10 80- lea d tqfp e- pa d pa cka g e: ja = 24 c/w (j ed e c std , 4- la yer p c b i n st i l l a i r ) jc = 16c/w maximum power dissipation the maxim u m p o w e r tha t can be s a f e l y dis s i p a t ed b y t h e ad8384 is limi ted b y i t s j u n c tion t e m p er a t ur e . the maxim u m s a fe j u n c t i on t e m p er a t ur e fo r plas t i c e n ca ps u l a t e d de vices, as d e t e rm in e d b y th e g l a s s tra n si tio n t e m p e r a t ur e o f th e p l as ti c, i s a p p r o x ima t e l y 150c. e x ceeding this limi t t e m p o r a r il y ma y ca us e a shif t in t h e p a ram e t r ic p e r f o r ma n c e d u e t o a cha n ge in t h e s t r e ss es exer t e d on t h e di e b y t h e p a cka g e . e x ce e d in g a j u n c tion t e m p er a t ur e o f 175c fo r a n ext e n d e d p e r i o d can r e s u l t in de vice fa il ur e . operating temperature range a l t h o u g h t h e maxim u m s a fe o p era t in g j u n c t i on t e m p era t ur e is hig h er , th e ad8 384 is 100% t e s t ed a t a j u n c tion t e m p era t ur e o f 125c. c o n s eq u e n t l y , th e maxim u m g u a r a n t e e d o p era t in g j u n c tion t e m p er a t ur e is 125c. t o en sur e op era t io n wi t h in t h e sp e c if ie d t e m p e r a t ur e ra n g e , i t i s n e ce ss a r y to limi t t h e max i m u m p o w e r dissi p a t i o n as fol l o w s: ) ( 5 . 0 C ) C ( lfm airflow t t p ja a jmax dmax overloa d protec tio n the ad8384 em p l o y s a 2-s t a g e o v erlo ad p r o t ec tio n cir c ui t tha t co n s ists o f an ou t p ut c u r r en t limi ter and a t h er ma l sh utdo w n . the maxim u m c u r r en t a t an y on e o u t p u t o f th e ad8384 is, o n a v e r age, i n te r n a l ly l i mi te d to 1 0 0 ma . in t h e e v e n t of a mome n - t a r y s h o r t cir c ui t b e tw e e n a vi de o o u t p u t and a p o w e r s u p p ly ra i l (v c c o r a g nd), t h e o u t p u t c u r r en t limi t is s u f f i cien t l y lo w to prov i d e te m p or ar y prote c t i on . the t h er mal s h u t do wn deb i as e s t h e o u t p u t am plif ier wh e n t h e j u n c t i on t e m p er a t ur e r e ach e s t h e in ter n al ly s e t t r i p p o in t. i n t h e e v en t o f a n ext e n d e d sh o r t-cir c ui t b e twe e n a vi de o o u t p u t an d a po w e r s u p p l y ra il , th e o u t p u t am p l if ier cur r en t co n t in ues t o swi t ch b e tween 0 ma and 100 ma typ i cal wi th a p e r i o d det e r - mi n e d b y t h e t h er mal t i m e co n s t a n t an d t h e h y st er esis o f t h e t h er mal t r i p p o i n t. th er mal sh u t do wn p r o v ides lo n g t e r m p r o- t e c t io n b y limi t i n g a v era g e j u n c t i o n t e m p er a t ure t o a s a fe le ve l. expose d p a ddle t o en sur e op t i mi ze d t h er ma l p e r f o r man c e, t h e ex p o s e d p a dd l e m u s t be t h er m a l l y co nn ec ted t o a n ext e r n al p l an e , s u ch as a v c c o r gnd , as des c r i b e d in t h e a pplic a t io n n o t e s. m a xim u m pow e r d i ssipa tion ( w ) 1.0 2.0 1.5 2.5 85 80 70 75 65 9 0 95 10 0 105 ambient temperature (c) 04512-0-002 100mhz 60hz xga quiescent still air 200lfm 500lfm f i gure 2. m a xi m u m p o wer d i s s i pat i on v s . t e mpe r atu r e* *a d8384 on a 4-l a y e r je d e c pc b with thermal l y optimiz ed l a nd ing pattern, as desc ri bed i n t h e ap pl ication notes . no t e : w h en o p era t in g u n der t h e condi t ion s sp e c if ie d in t h is da ta s h eet, t h e ad8384 s q u ies c en t p o w e r dis s i p a t io n is 1.1 w . w h en dr i v in g a 6-c h a n n e l x g a p a n e l wi th a 15 0 pf in p u t ca p a c i tan c e , t h e ad8384 dis s i p a t es a t o tal o f 1. 58 w w h en displ a y i ng 1-pixel- wid e a l ter n a t in g w h i t e an d b l ack v e r t ica l l i ne s ge ne r a te d b y a st a n d a rd 6 0 hz x g a i n put v i d e o . whe n t h e p i xe l c l o c k f r eq uen c y is ra is ed to 100 mh z (the ad8384 s max i m u m sp e c i f ie d o p er a t in g f r e q uen c y ) , to t a l p o wer dis s i p a t io n in creas e s t o 1.83 w . f i gur e 2 s h o w s th es e s p ecif ic po w e r d i s s i p a t io n s .
ad8384 rev. 0 | page 9 of 2 4 pin conf iguration and fu nction descriptions nc = no connect dgnd tstm clk xfr stsq inv r/l e/o sdi sen scl nc agnds svrl svrh vao1 vao2 avccs dirxin diryin dy in cly i n dirx diry dy cly cly n av ccl nrgin nrg mo niti nc mo nito dx in e nbx 1 i n agndl e nbx 2 i n e nbx 3 i n e nbx 4 i n clx i n agnd0 vid0 avcc0,1 vid1 agnd1,2 vid2 avcc2,3 vid3 agnd3,4 vid4 avcc4,5 vid5 agnd5 clxn clx enbx4 enbx3 enbx2 enbx1 dx dv cc db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 nc nc agndda c av ccdac vr h vr l v2 v1 by p 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 12 17 18 20 19 80 79 78 77 76 71 70 69 68 67 66 65 75 74 73 72 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 pin 1 identifier top view (not to scale) ad8384 f i g u re 3. 80-l e ad 1 2 mm 12 m m t q fp e - p a d pin conf i g ur at i o n ta ble 7. pi n f u nct i on d e s c ri pt i o ns pin name function description db(0:9) data input 10-bit da ta input. msb = db(9). c l k c l o c k c l o c k in p u t . s t s q s t a r t s e q u e n c e the state of sts q is detected on the active edge of clk. a new d a ta loading sequence begins on the next active edge of clk after sts q is detected hi gh. the active clk edge is the rising edge when e/ o is held high. it i s the falling edge when e/o is held low . r / l r i g h t / l e f t s e l e c t a new d a ta load ing sequence b e gins on the left , with channel 0, when this input is low, and on the right, with channel 5, when this in put is high. e / o e v e n / o d d s e l e c t the active clk edge is the rising edge when this input is held high. it is the falling edge when this input is held low. data is load ed se quentially on the ri sing ed ges of clk when this input is high and on the falli ng edges whe n this input is low. x f r d a t a t r a n s f e r xfr is detected and a data transf er is initiated on a rising clk e d ge when this input is held high. data is tra n sferred to the video outputs on the nex t rising clk edge after xfr is detected. vid0Cvid5 analog outputs these pins ar e directly connecte d to the an alog inputs of the lcd panel. v1, v2 reference voltages the voltage app l ied between v1 and agnd sets the white video level during inv = low. the voltage app l ied between v2 and agnd sets the white video level during inv = high. vrh, vrl full-scale references twice the volta g e applied betw een these pin s sets the full-scale video output v o ltage. byp bypass a 0.1 f capacitor conne cted between th is pin a n d agnd ensur e s optimum settling time.
ad8384 rev. 0 | page 10 of 24 pin name function description inv invert when this input is high, the vi dx output voltages are above v2 . when inv is low, the vidx output voltages are below v1. the state of inv is latched on the first risi ng clk edge, after xfr is detected. the vidx outputs change on the rising clk edge after the next xfr is detected. dvcc digital power supply digital power supply. dgnd digital ground this pin is normally connected to the digital ground plane. avccx analog power supplies analog power supplies. agndx analog ground analog supply returns. svrh, svrl serial dac reference voltages reference voltages for the output amplifiers of the control dacs. scl serial data clock serial data clock. sdi data input while the sen input is low, one 12-bit serial word is loaded into the serial dac on the rising edges of scl. the first bit selects the output, the next three bits are unused, and the subsequent eight bits are the data used in the dac. sen serial dac enable a falling edge of this input initiates a loading cy cle. while this input is held low, the serial dac is enabled and data is loaded on every ri sing edge of scl. the selected output is updated on the rising edge of this input. while this input is held high, the control dac is disabled. vao1, vao2 serial dac voltage output these output voltages are updated on the rising edge of the sen input. tstm test mode when this input is low, the output mode is determined by the function programmed into the serial interface. while this input is held high, the output mode is forced to normal, regardless of function programmed into the serial interface. moniti monitor input logic input of the level shifting inverting edge detector. monito monitor outp ut output of the level shifti ng inverting edge detector. dyin, diryin, dirxin, dxin, nrgin, enbx(1C4)in inverting level shifter inputs logic input of the inverting level shifters. dx, dy, dirx, diry, nrg, enbx(1-4) inverting level shifter outputs while the corresponding input voltage of th ese level shifters is below the threshold voltage, the output voltage at these pins is at voh. while the corresponding input voltage of th ese level shifters is above the threshold voltage, the output voltage at these pins is at vol. clxin, clyin complementary level shifter inputs logic input of the complementary level shifters. clx, clxn, cly, clyn, complementary level shifter outputs while the corresponding input voltage of th ese level shifters is below the threshold voltage, the voltage at the noninverting outp ut pins is at voh and the voltage at the inverting outputs is at vol. while the corresponding input voltage of th ese level shifters is above the threshold voltage, the voltage at the noninverting outp ut pins is at vol and the voltage at the inverting outputs is at voh.
ad8384 rev. 0 | page 11 of 24 timing characteristics decdriver section vrh vrl vid2 vid3 vid4 vid5 vid1 vid0 ad8384 byp r/l clk stsq xfr inv v1 v2 db(0:9) 2-stage 2-stage 2-stage 2-stage 2-stage 2-stage latch latch latch latch latch latch 10 10 10 10 10 10 10 10 10 10 10 10 scaling control sequence inv control control bias 10 10 dac dac dac dac dac dac 04512-0-004 f i gur e 4 . bl oc k diagr a m t f clk db(0:9) stsq xfr 04512-0-005 v th v th v th v th t r t 8 t 7 t 2 t 1 t 4 t 3 t 6 t 5 f i gure 5. input t i m i ng , even mod e (e / o = high) clk db(0:9) stsq xfr v th v th v th v th t 8 t 7 t 2 t 1 t 4 t 3 t 6 t 5 04512-0-006 f i gure 6. input t i ming , o dd m o de ( e/o = l o w ) clk stsq xfr inv v id(0:5) t 10 t 9 v2 50% pixels ? 6 ,? 5 , ? 4 ,? 3 , ? 2 ,? 1 v1 v1 ? vfs v2+vfs db(0:9) ?1 0 1 2 3 4 5 7 6 ?8 ? 7 ?6 ?5 ? 4 ?2 ?3 t 9 50% 04512-0-007 pixels 0, 1, 2, 3, 4, 5 f i gure 7. o u tput ti ming (r/l = l o w , e / o = high) table 8. timin g characteristics p a r a m e t e r c o n d i t i o n s m i n t y p m a x u n i t t 1 clk to data set u p time 0 ns t 2 clk to data hold time 3 ns t 3 clk to stsq setup time 0 ns t 4 clk to stsq hold time 3 ns t 5 clk to xfr set u p time 0 ns t 6 clk to xfr hold time 3 ns t 7 clk high time 3 ns t 8 clk low time 2.5 ns t 9 clk to vidx delay 10 12 14 ns t 10 inv to vidx delay 13 15 17 ns
ad8384 rev. 0 | page 12 of 24 level shifter section dyin diryin dirxin nrgin dxin enbx1in enbx2in enbx3in enbx4in dy diry dirx nrg dx enbx1 enbx2 enbx3 enbx4 04512-0-008 figure 8. level shifterinverting clxin clyin clx cly clxn clyn 04512-0-009 figure 9. level shiftercomplementary inverting outputs noninverting outputs inputs 04512-0-010 t 11 t 13 t 12 t 16 t 18 t 14 t 15 t 17 figure 10. inverting and complementary level shifter timing table 9. level shifter timing parameter conditions min typ max unit output rise, fall times, t r , t f t a min to t a max dx, clx, clxn, enbx(1C4) c l = 40 pf 18.5 30 ns dy, cly, clyn 40 70 ns dirx, diry 100 150 ns nrg c l = 200 pf 35 50 ns c l = 300 pf 55 100 ns propagation delay timest 11 , t 12 , t 13 , t 14 t a min to t a max dx, clx, clxn, enbx(1C4) c l = 40 pf 20 50 ns dy, cly, clyn 29 50 ns dirx, diry 60 100 ns nrg c l = 200 pf 25 55 ns c l = 300 pf 32 ns propagation delay skew t a min to t a max , c l = 40 pf enbx(1C4)t 15 , t 16 2 ns dx to enbx(1C4)t 16 2 ns dx to clxt 15 , t 16 , t 17 , t 18 10 ns dy to cly, clynt 15 , t 16 , t 17 , t 18 20 ns
ad8384 rev. 0 | page 13 of 24 level shifting edge detector moniti monito s r 04512-0-011 figure 11. level shifting edge detector block diagram monito moniti agnd avcc vol voh t 19 t 20 04512-0-012 figure 12. level shifting edge detector timing table 10. level shifting edge detector, avcc = 15.5 v, dvcc = 3.3 v, c l = 10 pf, t a min = 25c, t a max = 85c parameter min typ max unit v il input low voltage agnd agnd + 2.75 v v ih input high voltage avcc C 2.7 avcc v v th lh input rising edge threshold voltage agnd + 3 v v th hl input falling edge threshold voltage avcc C 3 v i ih input current high state 1.2 2.5 a i il input current low state C2.5 C1.2 a v oh output high voltage dvcc C 0.45 dvcc C 0.25 v v ol output low voltage 0.25 0.45 v t 19 input rising edge propagation delay time 16 ns ?t 19 t 19 variation with temperature 2 ns t 20 input falling edge propagation delay time 12 ns ?t 20 t 20 variation with temperature 2 ns t r output rise time 5 ns t f output fall time 6 ns
ad8384 rev. 0 | page 14 of 24 serial interface svrh svrl sdi scl sen tstm 12-bit shift register sd0 sd1 sd2 sd3 sd4 sd5 sd6 sd7 sd8 sd9 sd10 sd11 sd(0:7) 8 / enable thermal switch 6 / video dacs dual sdac select load control vao1, vao2 = svrl + sdicode (svrh?svrl)/256 6 / ao2 ao1 vid(0:5) 04512-0-013 6 / f i g u re 13. s e ri al int e r f ace b l o c k d i ag r a m scl sen sdi d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 04512- 0- 014 v ao1, v ao2 sen scl sdi v ao1, v ao2 t 20 t 24 t 25 t 26 t 21 t 22 t 23 d11 d0 d1 d10 04512- 0- 015 f i gure 14. s e ri al d a c t i mi ng table 11. serial dac ti ming p a r a m e t e r c o n d i t i o n s m i n t y p m a x u n i t sen to scl setup time, t 20 1 0 n s scl, high level pulse width, t 21 1 5 n s scl, low level pulse width, t 22 1 0 n s sdi setup time, t 24 1 0 n s sdi hold time, t 25 1 0 n s scl to sen hold time, t 23 1 5 n s vao1, vao2 set t ling time, t 26 vfs = 5 v, to 0.5 % , c l = 100 pf 1 2 s vfs = 5 v, to 0.5 % , c l = 33 f 10 15 ms
ad8384 rev. 0 | page 15 of 24 functional description the ad8384 is a sys t em b u il din g b l o c k desig n ed t o dir e c t l y dr i v e t h e col u mn s o f l c d micro d is pl a y s o f t h e typ e p o p u la r i ze d fo r us e in p r o j e c t i on sys t ems. i t co m p r i s e s six c h a n n e ls o f p r ecisio n, 10-b i t dig i tal-t o -a nalog co n v er t e rs lo aded f r o m a sin g le , hi g h sp e e d , 10- b i t wide in p u t. pr e c isio n c u r r en t fe e d b a ck am plif iers, p r o v idin g w e l l - d am p e d pu ls e r e sp o n s e and fas t v o l t a g e s e t t l i n g i n t o la rg e c a p a ci t i v e lo ads, b u f f er t h e six o u t p u t s. l a s e r tr immin g a t t h e wa f e r lev e l ens u r e s lo w a b s o l u t e output e r rors an d t i g h t ch an n e l - to - c h a n n el m a tch i n g . t i g h t p a r t -t o-p a r t m a t c hin g in high r e so l u tio n sys t em s is gua r an t e e d b y t h e us e o f ext e r n al v o l t a g e r e fer e n c es. thr e e g r o u ps o f lev e l s h if t e rs con v er t dig i tal in p u ts t o hig h vol t a g e o u t p uts fo r dir e c t co nne c t io n to t h e co n t r o l in p u ts o f lc d p a nel s . a n e d ge d e te c t o r c o nd it i o ns a h i g h vo lt age re fe re nc e t i m i ng in p u t f r o m th e l c d and co n v er ts i t t o dig i tal l e v e ls f o r use in a syn c hr o n izin g t i min g con t r o l l er s u c h as the ad8389. start s e quence controlin put data loading a va lid s t sq c o n t r o l in p u t ini t ia t e s a ne w 6 - clo c k lo adin g c y cle d u r i n g w h ich si x in p u t da t a -w or ds a r e lo ade d s e q u en t i a l ly in t o six in ter n a l channels. a n e w lo adin g s e q u e n ce b e g i n s o n t h e c u r r en t ac ti v e clk edge o n l y w h en s t sq was h e l d hi gh a t th e p r eced in g a c ti v e c l k e d g e . right/left controlinpu t da ta lo a d i ng t o faci l i t a t e image mir r o r in g, t h e dir e c t ion o f t h e lo adin g seq u en c e i s set b y th e r / l c o n t r o l . a ne w lo ad in g s e q u ence b e g i n s a t c h an n e l 0 and p r o c e e d s to cha n n e l 5 w h en the r/l co n t rol is h e l d l o w . i t beg i n s a t cha n n e l 5 and p r o c eeds t o channe l 0 w h en t h e r/l con t r o l is hel d h i g h . even/odd controlin put data loading d a t a is lo ade d on t h e r i sin g cl k e d ges w h en t h is in p u t is hi gh, an d on t h e fa l l i n g cl k e d ges w h e n t h is in p u t is l o w . xfr controldat a t r ansfer to out p uts d a t a t r a n sfer t o t h e o u t p u t s is i n i t ia t e d b y t h e xfr co n t r o l. d a t a is t r a n sfer r e d t o al l o u t p u t s sim u l t a n e o us l y o n t h e r i sin g cl k ed g e o n l y wh en x f r w a s hi gh d u ri n g t h e p r eced in g ri s i n g clk e d ge . v1, v2 inputs voltage reference in puts t w o ext e r n al a n alog v o l t a g e r e fer e n c es s e t t h e le v e ls o f t h e o u t p u t s. v1 s e ts t h e o u t p u t v o l t a g e a t c o de 102 3 whi l e t h e i n v in p u t is l o w ; v2 s e ts t h e o u t p u t v o l t a g e a t c o de 1023 while inv is h e l d hi gh. vrh, vrl inputsfull-scale video r e feren c e inputs t w ic e t h e dif f er en c e b e tw e e n t h es e a n alog in pu t v o l t a g es s e ts t h e f u l l -s ca le o u t p u t v o lt a g e vfs = 2 (vrh C vrl). inv control analog o u tp ut in version the a n alog v o l t a g e e q u i valen t of t h e in p u t co de is s u b t r ac te d f r o m ( v 2 + vf s) w h i l e in v is held hi g h and a dde d to (v1 Cvfs) wh ile in v is h e ld lo w . v i d e o in v e r s io n is d e la y e d b y six t o 12 clk c y cles f r o m th e i n v i n p u t. trans f er f u n c tion an d an al og out p ut vol t age the d e cdr i v e r has tw o r e g i o n s o f o p era t io n w h er e t h e vide o o u t p u t v o l t a g es a r e ei t h er a b o v e r e fer e n c e v o l t ag e v2 or b e l o w re f e re nc e vo lt ag e v1 . th e t r a n sfer f u n c t i o n def i n e s t h e vide o o u t p u t v o l t a g e as a fu n c ti o n o f th e d i gi tal i n p u t cod e : vid x ( n ) = v2 + vfs (1 C [ n /1023]), f o r inv = hi gh vid x ( n ) = v1 - vfs (1 C [ n /1023]), f o r inv = l o w wher e: n = in p u t co de vfs = 2 ( vr h C vrl ) a n u m b er o f in t e r n al limi t s def i ne t h e us a b le ra n g e o f t h e vi de o o u t p u t v o l t a g e s , v i d x . s e e f i g u r e 1 5 . input code vid x ( v ) agnd v1 ? v f s v1 v2 v2 + v f s avcc 0 1023 04512-0-016 0 vfs 5.5v 0 vfs 5.5v 5.25v v2 ( avcc ? 4) 5.25v v1 ( avcc ? 4) 9v avcc 18v 1.3v 1.3v inv = high voutn(n) voutp(n) inv = low internal limits and usable voltage ranges f i g u re 15. t r ans f er f u nc t i on and u s ab le v o lt ag e r a ng es
ad8384 rev. 0 | page 16 of 24 accuracy t o b e s t co r r e l a t e t r a n sfer f u n c t i o n er r o rs t o ima g e a r t i fac t s, t h e o v erall accurac y o f th e decdr i ver is d e f i n e d b y tw o pa ra m e t e r s : vd e a n d v c m e . vd e, t h e dif f er en t i al er r o r v o l t a g e , m e as ur es t h e dif f er en ce b e tw e e n t h e r m s val u e o f t h e ou t p u t an d t h e r m s val u e o f t h e ide a l. th e def i ni n g exp r es sio n is vfs n 1 v n voutp 2 v n voutn n vde ? ? ? ? ? ? = 1023 C 1 C 2 ] C ) ( [ C ] C ) ( [ ) ( v c me, t h e co mm on- m o d e er r o r v o l t a g e , me as u r es ? t h e dc b i as o f t h e o u t p u t . th e def i nin g exp r es sio n is () ? ? ? ? ? ? + + = 2 1 2 C 2 ) ( ) ( 2 1 ) ( v v n voutp n voutn n vcme tstm c o n t roltest mode a l o w on t h is in p u t a l lo ws s e r i a l i n t e r f ace con t r o l o f t h e output op e r a t i n g mo d e . a h i g h on t h i s i n put f o rc e s t h e v i d e o o u t p uts an d v a o1 to n o r m a l op er a t i n g m o de. grounde d outpu t mo de i n n o r m al o p er a t in g mo de , t h e v o l t a g e o f t h e v i de o o u t p u t s and v a o1 a r e det e r m i n e d b y t h e i n p u ts. i n gr o u nde d o u t p ut m o de, t h e vide o o u t p uts and v a o1 a r e fo r c e d to a g n d . overloa d protec tio n t h e ove r l o a d prote c t i on e m pl oy s c u r r e n t l i m i te r s an d a t h e r m a l s w i t ch , p r o t ectin g th e v i d e o o u t p u t p i n s a g a i n s t a cci d e n t al shor t s b e t w e e n an y v i d e o output pi n a n d a v c c or a g n d . the j u n c t i o n te m p er a t ur e t r i p p o in t o f t h e t h e r mal swi t ch is 165c. p r o d uc tio n t e s t g u a r an t e es a m i nim u m j u n c tion t e m p era t ur e tr i p p o in t o f 125c. c o n s eq uen t ly , th e o p er a t in g j u n c tion t e m p er a t ur e sh o u l d n o t be al lo w e d t o r i s e a b o v e 125c. f o r syst em s t h a t o p era t e a t hig h in t e r n al am b i en t t e m p era t ur es a n d r e q u ir e l a rg e ca p a c i ti v e lo ads t o be dr i v en b y th e ad8384 a t hig h f r eq uen c ies, a m i nim u m a i r f l o w o f 200 l f m s h o u ld be m a in ta in e d t o en s u r e j u n c tion tem p er a t ur es be l o w 125c. 3-wire seri al interface the s e r i al in ter f ace co n t r o ls two 8-b i t s e r i al d a cs, t h e o v erlo ad prote c t i on a n d t h e v i d e o output op e r a t i n g mo d e v i a a 1 2 - bit w i d e s e r i a l wor d f r om a m i c r o p ro c e ss or . f o u r of t h e 1 2 - bit s s e le c t t h e f u n c t i o n an d t h e r e ma inin g eig h t b i ts a r e t h e da t a fo r th e se r i al d a cs. tab l e 12. bit defin i tion s bit n a m e b i t f u n c t i o n a l i t y sd(0:7) 8-bit sdac data . msb = sd7. s d 8 n o t u s e d . s d 9 n o t u s e d . sd10 output operating mode an d sdac selection c o ntrol. sd11 output operating mode an d sdac selection c o ntrol. table 13. truth table sd s e n 1 1 1 0 9 8 actio n 0 0 x x load vao2. no change to vao1. no change to grounded mode. 1 0 x x load vao1. release outputs from grounded mod e . no change to ao2. 0 1 x x release video outputs and vao 1 from grounded output mode. n o change to vao1 and vao2 data. 1 1 x x video outputs a n d vao1 to grounded outp ut mode. no ch ange to vao1 and va o2 data. x x x x no c h a n g e . serial dac s b o t h s e r i a l d a cs a r e lo ade d v i a t h e s e r i a l i n ter f ace. th e o u t p ut v o l t a g e is de t e r m i n e d b y t h e fol l o w in g e q u a t i on: va o 1 , v ao 2 = svrl + sd (0:7) ( svrh C svrl )/256 ou t p u t v ao 1 is design e d t o dr iv e v e r y la r g e ca p a ci ti v e lo ads a b o v e 0.047 f . lo w e r ca p a c i ti ve lo ads m a y r e s u l t in exces s i v e ove r sho o t at v ao 1 . level shif ters the cha r ac t e r i st ics o f t h e le ve l shif t e rs a r e o p t i mi ze d b a s e d on th e i r in t e n d ed use . s e v e n leve l s h if tersd x, clx, clxn, a n d e n bx(1:4)a r e o p t i mi ze d fo r x dir e c t ion, and t h r e ed y , c l y , a n d cl yn a r e o p t i mize d fo r t h e y dir e c t i o n co n t r o l sig n als. on e le ve l s h if t e r , n r g, is design e d t o dr i v e a la r g e c a p a c i t i v e lo ad an d o p t i mi ze d fo r a n x d i r e c t io n con t r o l sig n a l an d tw o , d i r x an d d i r y a r e o p timize d f o r v e r y lo w f r eq uen c y con t r o l sig n als. on e l e vel shif t i n g e d ge dete c t or , moni ti , mo ni t o , is o p t i mi ze d to con d i t ion a s y nch r o n izi n g fe e d b a ck r e fer e n c e sig n al f r o m t h e l c d .
ad8384 rev. 0 | page 17 of 24 appli c ations image processor 1/3 ad8389 clk dxi, clxi, enbx(1?4)i dxxo, clxxo, enbx(1? 4)xo monitxi p ad8384 vid(0:5) db(0:5) stsq, xfr, clk, r/l, inv dirx, diry, dy, cly, clyn, nrg dirxin, diryin, dyin, clyin, nrgin moniti monito dx, clx, clxn, enbx (1? 4 ) dxin, clxin, enbxin (1?4) sdi scl sen vao1 vao2 04512-0-017 vrh, vrl, v1, v2, svrh, svrl dc reference voltages monitor vcom lcd timing controls lcd timing controls 6-channel lcd channel 0?5 f i gure 16. t y pic a l a p plic at ions c i r c u i t power supply sequencing a s i n dic a te d u n der t h e a b s o l u te m a x i m u m r a t i n g s, t h e vol t a g e a t an y in p u t p i n ca nn o t ex cee d i t s s u p p l y v o l t a g e b y m o r e than 0.5 v . t o ens u r e co m p lian ce wi t h the a b s o l u t e m a xim u m r a tin g s , th e f o llo w i n g po w e r - u p a n d po w e r - d o wn seq u en cin g is r e c o mme n d e d . d u r i n g p o w e r - u p , ini t ia l a p plic a t io n o f n o nzero v o l t a g es t o an y o f t h e in p u t pins m u st b e de l a ye d un t i l t h e su pply v o l t a g e ra m p s u p t o a t le ast t h e hig h est maxi m u m op era t io nal in p u t v o l t a g e . d u r i n g p o w e r - do wn, t h e v o l t age a t an y i n p u t p i n m u st r e ach zer o d u r i n g a p e r i o d n o t exce e d in g t h e h o ld-u p t i me o f t h e po w e r s u p p l y . power on s e q u e n ce t h e a pplie d v o l t a g es st a r t i n g wi t h t h e hig h e s t and p r oceed in g t o wa r d th e lo w e s t . a p p l y a v c c a n d th en p r oce e d wi t h a p plying t h e v o l t a g es i n a de cr e a sin g o r de r , fo r exa m ple vrh, v2, an d s o o n . a p ply d v c c la st. power off r e m o v e v o l t a g es s t a r ti n g w i t h t h e lo w e s t a n d p r oceed t o w a r d t h e hig h est. re m o v e d v c c and t h e n p r o c e e d wi t h t h e v o l t a g e s in an i n cr e a sin g o r der , fo r e x a m ple v1, v2, vrh, a n d s o o n . re m o v e a v c c last . f a i l ur e t o co m p ly wi t h t h e a b s o l u t e m a xim u m r a t i n g s ma y r e s u l t in f u n c tio n al fa il ur e o r dam a g e t o t h e in t e r n al es d dio d es. d a m a ge d es d dio d es m a y ca us e te m p o r a r y p a r a m e t r ic fa il ur e s , wh i c h m a y r e s u l t in im a g e a r ti fa ct s. da m a ged es d d i o d e s c a n n ot prov i d e f u l l e s d prote c t i on , re d u c i ng rel i abi l it y . to ensur e gro u n d e d out p ut mode at power- o ff i f re f e re nc e s are a c t i ve s o u r c e s : 1. pr o g r a m gr o u n d e d o u t p ut mo de 2. t u r n of f re f e re nc e s 3. t u rn o f f a v cc 4. tu r n o f f d v c c i f r e fer e n c es a r e p a ssi v e v o l t a g e dividers de p e n d en t on a v c c : 1. pr o g r a m gr o u n d e d o u t p ut mo de 2. se t a v cc t o 5 v 3. ho l d f o r 1 m s 4. tu r n o f f d v c c 5. t u rn o f f a v cc
ad8384 rev. 0 | page 18 of 24 vbias gene ratio n v 1, v2 inpu t pin func tio n a l ity i n o r der t o a v o i d ima g e f l ick e r , a symm et r i c a l ac v o l t a g e is r e q u ir e d and a b i as v o l t a g e o f a p p r o x ima t ely 1 v mini m u m m u s t be m a in t a in e d acr o s s the p i x e ls o f ht ps lcd s . th e ad8384 p r o v ides tw o m e tho d s o f m a in taining this b i as v o l t a g e . inter n al bi as voltage g e ne ration s t a n da rd sys t em s t h a t in t e r n al l y g e n e ra t e t h e b i as v o l t a g e r e s e r v e t h e u p p e r - m o st co de ran g e fo r t h e b i as v o l t a g e , and us e t h e r e maining c o de ra n g e t o enco de t h e vide o fo r ga mma co r r e c t i o n . i n t h es e syst em s, a hig h deg r e e o f ac symm et r y is gua ra n t ee d b y th e ad8384. the v1 and v2 in p u ts in t h es e s y st em s a r e t i e d tog e t h er an d a r e n o r m al l y co nne c t ed t o v c o m , as sh o w n in f i gur e 17. vbias = 1v vcom vf s = 5 v vfs = 5v reserved code range vbias = 1v v2 v1 vcom ad8384 04512- 0- 018 1023 820 f i gur e 1 7 . v1 , v 2 co nnecti o n and t r ansfe r f u ncti on in a t y pic a l st and a r d sy s t em extern al bias voltage g e ne ration i n syst e m s t h a t r e q u ir e im p r o v e d b r ig h t n e ss r e s o l u t i o n and hig h er acc u rac y , t h e v1 and v2 i n p u ts, co nne c t e d t o ext e r n al v o l t a g e r e fer e n c es, p r o v ide t h e n e ce ss a r y b i as vol t a g e (v b i a s ) whi l e al lo wi n g t h e f u l l co de ra ng e t o b e us e d fo r ga mma co r r ec tio n . t o en sur e a symm et r i cal ac v o lt a g e a t t h e o u t p u t s o f t h e ad8384, vb i a s m u s t r e m a in con s tan t fo r bo t h s t a t es o f inv . ther efo r e , v1 a n d v2 a r e def i ne d as v1 = vc om C vbi a s v2 = vc om + vbi a s applic ati o ns circuit the cir c ui t i n f i gur e 18 en sur e s vb i a s symm et r y t o wi t h in 1 mv wi t h a mi nim u m c o m p on e n t c o u n t. by p a ss c a p a c i to rs ar e not sho w n f o r c l ar it y . n o t e f r o m t h e c u r v e in f i gur e 20 tha t t h e ad81 32 (f igur e 18) typ i cal l y p r o d uces a symm et r i c a l o u t p u t a t 85 c when i t s s u p p l y , (v+) C ( v C), is a t 7.2 v . avcc = 15.5v vz = 5.1v dvcc = 3.3v 04512-0-019 v com = 7v r1 = 6k ? r2 = 1k ? v2 = 8v v1 = 6v v2 v1 ad8384 ad8132 6 3 2 1 8 v? v+ v com ?in +in 5 4 f i g u re 18. e x ter n a l v b ia s gener a to r with the ad813 2 vbias = 1v vcom v2 v1 vf s = 4v vfs = 4v vbias = 1v 1023 04512-0-025 f i gure 19. a d 8 3 8 4 t r a n sfer f u nc ti on i n a t y pi c a l high ac cur a c y s y stem 5.7 6.2 6.7 7.2 7.7 8.2 8.7 9.2 9.7 10.2 10.7 ?8.75 ?6.25 ?3.75 1.25 3.75 6.25 7.50 8.75 ?1.25 ?7.50 ?5.00 0.00 2.50 5.00 ?2.50 [v+] ? [v? ] (v) (v 2 + v 1 )/ 2 ? v c o m (mv ) 04512-0-020 t a = 85c t a = 25c f i gure 2 0 . t y pi c a l a s ym m e tr y a t the o u tputs o f the ad813 2 vs . its p o wer sup p ly f o r t h e a p pl ic at io n ci r c u i t
ad8384 rev. 0 | page 19 of 24 pcb design for optimized thermal performance the ad8384s total maximum power dissipation is partly load dependent. in a 6-channel 60hz xga system running at a 65 mhz clock rate, the total maximum power dissipation is 1.6 w at a 150 pf lcd input capacitance. at a clock rate of 100 mhz, the total maximum power dissipation can exceed 2 w, as shown in table 14, for a black-to- white video output voltage swing of 4 v and 5 v. table 14. power dissipation v swing = 5 v v swing = 4 v c load (pf) p quiescent (w) p dynamic (w) p total (w) p dynamic (w) p total (w) 150 1.12 0.82 1.94 0.71 1.83 200 1.12 1.01 2.13 0.86 1.98 250 1.12 1.21 2.33 1.01 2.13 300 1.12 1.41 2.53 1.17 2.29 although the maximum safe operating junction temperature is higher, the ad8384 is 100% tested at a junction temperature of 125c. consequently, the maximum guaranteed operating junction temperature is 125c. to limit the maximum junction temperature at or below the guaranteed maximum, the package, in conjunction with the pcb, must effectively conduct heat away from the junction. the ad8384 package is designed to provide enhanced thermal characteristics through the exposed die paddle on the bottom surface of the package. in order to take full advantage of this feature, the exposed paddle must be in direct thermal contact with the pcb, which then serves as a heat sink. a thermally effective pcb must incorporate two thermal pads and a thermal via structure. the thermal pad on the top surface of the pcb provides a solderable contact surface on the top surface of the pcb. the thermal pad on the bottom pcb layer provides a surface in direct contact with the ambient. the thermal via structure provides a thermal path to the inner and bottom layers of the pcb to remove heat. thermal pad design to minimize thermal performance degradation of production pcbs, the contact area between the thermal pad and the pcb should be maximized. therefore, the size of the thermal pad on the top pcb layer should match the exposed paddle. the second thermal pad of the same size should be placed on the bottom side of the pcb. at least one thermal pad should be in direct thermal contact with an external plane such as avcc or gnd. thermal via structure design effective heat transfer from the top to the inner and bottom layers of the pcb requires thermal vias incorporated into the thermal pad design. thermal performance increases logarithmically with the number of vias. near optimum thermal performance of production pcbs is attained only when tightly spaced thermal vias are placed on the full extent of the thermal pad.
ad8384 rev. 0 | page 20 of 24 ad8384 pcb design recommendations top pcb lay e r land patt ern dimensions pa d s i z e : 0.6 mm 0.25 m m pa d p i t c h : 0.5 m m ther ma l p a d s i z e : 6 mm 6 mm ther ma l v i a str u c t ure: 0.25 mm t o 0.35 mm diam eter via h o les o n a 0.5 m m t o 1.0 m m g r id . 14 mm 14 mm land pattern ? top layer 04512-0-021 6 mm 6 m m f i gure 21. land p a t t ern? t o p laye r bottom pcb layer ther m al pa d an d th er mal via c o nn ectio n s the t h er mal p a d o n t h e s o lder side is co nn e c te d t o a pl an e . u s e o f t h er mal sp ok es is n o t r e comm e n de d when conn e c t i n g t h e t h er mal p a ds o r vi a st r u c t ur e t o t h e plan e . land pattern ? bottom layer 04512-0-022 6 mm 6 m m f i gure 22. land p a t t ern ? bottom laye r solder mas k ing s o lder maski n g o f t h e v i a h o les o n t h e t o p l a yer o f t h e pcb pl ug s th e via h o les, in hib i tin g so lder f l o w in t o the h o l e s. t o m i nim i ze th e fo r m a t io n o f s o lder v o ids d u e t o s o lder f l o w in g i n t o t h e v i a h o les (s older wick ing ) , t h e v i a d i am eter sh o u ld b e ma de sma l l an d an opt i on a l s o l d e r m a sk m a y b e u s e d . t o opt i m i z e t h e r m a l p a d co v e ra g e , t h e s o lder mask s diam e t er sh o u ld b e n o m o r e t h a n 0.1 m m l a rg er tha n t h e via h o le diam et er . sold er masktop lay e r pa d s : s e t b y t h e c u s t o m er s p c b desig n r u les. ther ma l v i a h o l e s: cir c u l a r mask, ce n t er e d o n t h e v i a h o les. diam et er o f th e m a s k s h o u l d b e 0.1 m m l a rg er tha n t h e via h o le diamet er . sold er maskbottom lay e r s e t b y c u s t om er s pcb desig n r u les. solder mask ? top layer 04512-0-023 f i gure 23. s o ld er m a s k ? t op l a yer
ad8384 rev. 0 | page 21 of 24 outline dimensions 0.15 0.05 0.27 0.22 0.17 0.20 0.09 0.50 bsc gage plane 0.25 7 3.5 0 1.05 1.00 0.95 1 20 21 41 40 60 80 61 pin 1 top view (pins down) 14.00 sq 12.00 sq seating plane 1.20 max 0.75 0.60 0.45 1 20 21 41 40 60 80 61 6.00 sq bottom view coplanarity 0.08 compliant to jedec standards ms-026-add-hd figure 24. 80-lead, thermally enhanced thin quad flatpack package [tqfp] (sv-80) dimensions shown in millimeters esd caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discha rges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide model temperature range package description package option AD8384ASVZ 11 0c to 85c 80-lead thin quad flat pack sv-80 11 z = pb-free part.
ad8384 rev. 0 | page 22 of 24 notes
ad8384 rev. 0 | page 23 of 24 notes
ad8384 rev. 0 | page 24 of 24 notes ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . d04512C0C 1/04(0)

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